1. Field of the Invention
The invention generally relates to a display device, and more particularly, to a display controller driver for driving a display panel and a testing method thereof.
2. Description of Related Art
FIG. 1A is a block diagram of a conventional display controller driver. Referring to FIG. 1A, the conventional display controller driver 100 is connected to an external processor 110 and a display panel 140. The display controller driver 100 includes a system interface circuit 120, a memory control circuit 122, an image data memory 124, a timing control circuit 126, a shift register 128, a data line driving circuit 130, a grayscale voltage generating circuit 132, and a gate line driving circuit 134. The system interface circuit 120 is coupled to the external processor 110, and the data line driving circuit 130 and the gate line driving circuit 134 are coupled to the display panel 140.
When the display controller driver 100 works in a normal operation mode, the processor 110 sends display data to the memory control circuit 122 through the system interface circuit 120. The memory control circuit 122 temporarily stores the display data into the image data memory 124. The processor 110 sends control signals to the timing control circuit 126 through the system interface circuit 120. The timing control circuit 126 issues corresponding control signals to the memory control circuit 122, the shift register 128, the data line driving circuit 130, the gate line driving circuit 134, and the grayscale voltage generating circuit 132 in time sequence. The control flow is described below. The timing control circuit 126 reads image data from the image data memory 124 through the memory control circuit 122 and sends the image data to the shift register 128. The shift register 128 latches the image data according to a latch pulse of the timing control circuit 126 and sends the latched image data to the data line driving circuit 130. The timing control circuit 126 also issues control signals according to a predetermined timing to control the data line driving circuit 130 and the gate line driving circuit 134 to send the image data into pixels of the display panel 140, so as to display a corresponding image.
FIG. 1B is a timing diagram of a normal operation flow of the display controller driver 100. After display data in the first row is read from the image data memory 124 and input into the shift register 128, the timing control circuit 126 issues a latch enable signal to the data line driving circuit 130 to store the first row of display data into the data line driving circuit 130. After that, the timing control circuit 126 issues an output enable signal to the data line driving circuit 130 to output the first row of display data from the data line driving circuit 130 to the display panel 140 to display it. At the same time when the data line driving circuit 130 outputs the first row of display data, display data in the second row is read from the image data memory 124 and input into the shift register 128. During the next display cycle, the data line driving circuit 130 outputs the second row of display data. All the display data is output to the display panel 140 through the data line driving circuit 130 based on foregoing time sequence.
When a test operation is performed on the display controller driver 100, the display controller driver 100 works in a test operation mode, and the external processor 110 (for example, a test platform) needs to write a test pattern into the image data memory 124 beforehand through the system interface circuit 120 and the memory control circuit 122 to test the image data memory 124. Namely, in the test operation mode, the external processor 110 tests whether image data (i.e., the test pattern) can be correctly stored into the image data memory 124. Referring to FIG. 1C, in foregoing test operation mode, the entire transmission path of the test pattern includes a write path 112 and a read path 114. The write path 112 is sequentially composed of the processor 110, the system interface circuit 120, the memory control circuit 122, and the image data memory 124. The read path 114 is sequentially composed of the image data memory 124, the memory control circuit 122, the system interface circuit 120, and the processor 110. The test pattern is stored into the image data memory 124 through the write path 112, then read out from the image data memory 124, and sent to the processor 110 (for example, a test platform) through the read path 114.
FIG. 1D illustrates the entire test flow. First, in step S210, the external processor 110 writes the test pattern into the image data memory 124 via the write path 112. Then, in step S220, the external processor 110 reads the test pattern from the image data memory 124 via the read path 114 (i.e., the system interface circuit 120). Next, in step S230, the external processor 110 determines whether the test pattern read from the image data memory 124 matches a predetermined pattern. If the test pattern read from the image data memory 124 does not match the predetermined pattern (i.e., the test is not passed), the test flow ends in step S250. If the test pattern read from the image data memory 124 matches the predetermined pattern (i.e., the test is passed), in step S240, whether the test pattern is the last test pattern is determined. If it is determined in step S240 that the test pattern is the last test pattern, the test flow ends in step S250. If it is determined in step S240 that the test pattern is not the last test pattern, step S210 is executed again to test the next test pattern.
FIG. 2A is a timing diagram when the processor 110 writes test patterns into and reads test patterns from the display controller driver 100 having a QVGA resolution (i.e., 240×320), wherein the upper portion is the timing diagram of the writing operation, and the lower portion is the timing diagram of the reading operation. Referring to FIG. 2A, CSX, WRX, D/CX, and RDX are control signals issued by the processor 110 to the display controller driver 100. D is a bidirectional data bus connected between the processor 110 and the display controller driver 100. The control signal CSX is a chip selection signal, the control signal WRX is a write enable signal, the control signal D/CX indicates whether a current signal on the bidirectional data bus D is “command” or “data”, and the control signal RDX is a read enable signal. When a test pattern is written, the processor 110 sends a command (marked as “COMMAND” in FIG. 2A) and the test pattern (marked as “DATA” in FIG. 2A) to the display controller driver 100. When a test pattern is read, the display controller driver 100 sends the previously written test pattern to the processor 110.
A write cycle mentioned below refers to the time for writing a command or data, and a read cycle refers to the time for reading a data. The data marked with “DUMMY” in FIG. 2A is a redundant data instead of real data. Regarding a conventional display controller driver 100 having a QVGA resolution, the write cycle is 65 nanoseconds (ns), and the read cycle is 450 ns. Taking two test patterns as an example, the time (about 79 milliseconds (ms)) for executing one test operation can be calculated by using following formula:[65×(320×240+1)+65+(320×240+1)×450]×2=79105160 ns.
FIG. 2B is a timing diagram when the processor 110 writes test patterns into and reads test patterns from the display controller driver 100 having a WVGA resolution (i.e., 480×864), wherein the upper portion is the timing diagram of the writing operation, and the lower portion is the timing diagram of the reading operation. FIG. 2B can be referred to the descriptions related to FIG. 2A. When a test pattern is written, the processor 110 sends a command (marked as “COMMAND” in FIG. 2B) and the test pattern (marked as “DATA” in FIG. 2B) to the display controller driver 100. When a test pattern is read, the display controller driver 100 sends the previously written test pattern to the processor 110. Regarding a conventional display controller driver 100 having a WVGA resolution, the write cycle is 33 ns, and the read cycle is 400 ns. Taking two test patterns as an example, the time (about 359 ms) for executing one test operation can be calculated by using following formula:[33×(864×480+1)+33+(864×480+1)×400]×2=359148452 ns.
In the conventional display controller driver structure described above, when a test operation is performed on the display controller driver 100, the testing time cannot be shortened due to the communication protocol adopted by the transmission interface and the restriction of the single transmission channel (the bidirectional data bus D).